The present disclosure relates to methods of patterning a metallic material layer on a dielectric material layer and structures for effecting the same.
Patterning of a metallic material layer overlying a dielectric layer can result in collateral damages of the underlying dielectric layer. In case the functionality of the dielectric layer is affected by collateral damages as in the case of a gate dielectric layer, minimizing the collateral damages during the processing steps is critical in providing high performance and/or reliability in the device employing the dielectric layer.
For example, a patterning process for a stack of a high dielectric constant (high-k) gate dielectric layer including a dielectric metal oxide and a metallic material layer can employ an etch mask stack including a second metallic material layer in addition to a photoresist layer. While the second metallic material layer can be advantageously employed to generate a high fidelity replica of the pattern in the photoresist layer, removal of the second metallic material layer can result in collateral etch of the high-k gate dielectric layer and metallic contamination in a processing tool. Further, removal of additional materials in the etch mask stack can result in further collateral etching of the metallic material layer. Thus, a method is desired for patterning a metallic material layer while minimizing collateral etches of an underlying dielectric layer and avoiding metallic contamination.